Interleaving Test Algorithm for Detecting Defects in DRAM

Abstract

Since the minimum feature size of dynamic RAM has been down-scaled. Several studies have been carried out to determine ways to protect cell data from leakage current in many areas. In the field of testing, more appropriate test algorithms are required to detect weak cells with leakage-current sources. In this paper, we propose an interleaving test algorithm that takes into account the equal bit-line stress regardless of the cell location. The proposed test algorithm allows screening of weak cells and correct it due to the subthreshold leakage current.